Step 3: Charge Transfer
Figure 4.7: Basic charge transfer
in a 3-phase CCD.
Figure 4.8: Buried channel
MOS potential well.
Once charge has accumulated in each pixel it is necessary to transfer the charge to a point where it can be "detected". This is done by moving the potential minima [Boyle and Smith, 1970]. The method for a 3-phase architecture is illustrated in Figure 4.7. The position of the pixel is defined only by the relative potentials on each of the three phases during exposure. Note also that with the simple architecture described, at least three phases are required in order for the direction of charge transfer to be defined.
Before looking at other possibilities, it important to note that there are major shortcomings of the simple architecture described so far. Verification of Boyle’s CCD concept by Amelio et al.  resulted in charge being transferred with efficiencies of only about 98%. Using a 3-phase device. This would corresponds to almost a 50% loss over 10 pixels! The main reasons for the inefficiency are trapping of charge and anomalies in the potential profiles.
During charge transfer some of the electrons may be trapped at the Si/SiO2 boundary, resulting in a reduction in transfer efficiency. Modification of the basic surface channel CCD structure by the addition of an n-type layer of silicon, results in the potential well now occurring within the bulk of the silicon. With this buried channel structure, illustrated in Figure 4.8, trapping of charge is several orders of magnitude less than that for surface channel devices. This buried channel structure was originally proposed by Boyle and Smith in a patent application [see Walden et al., 1972].
Modern CCDs, such as the TC215 CCD, exhibit charge transfer efficiencies better than 99.99%. This is a significant improvement on the original devices.
The Number of Phases
As previously mentioned, at least three phases are required in order for the direction of charge transfer to be defined with many currently available CCD detectors, such as those from Scientific Imaging Technologies (SITe), being 3-phase devices. For video applications however it is desirable to have an even number of phases so that interlaced images may be easily produced.
A 4-phase CCD is substantially similar to that shown in Figure 4.7 except that a series of four gates are used rather than three, with the gates of two adjacent phases being high (more positive) at each time. The use of a 4-phase structure with only a single gate high at any one time is also possible however is rarely, if ever, used because of the resultant reduction in well capacity. Many of the early CCDs designed for video applications were 4-phase devices.
Consider now a 4-phase structure where phase 2 gate is always slightly more positive than phase 1 gate and similarly for phases 4 and 3. These small applied potential differences provide sufficient bias to define the direction of charge transfer in what is now pseudo 2-phase system. In practical 2-phase CCDs, which are common in video applications, ion implants beneath part of each gate structure are used to distort the the potential profile and allow a true 2-phase structure.
Figure 4.9: The evolution from 4-phase to virtual phase CCDs.
The idea of using ion implants to modify the potential profiles can be carried one step further. A 2-phase CCD may be operated in a 1.5 phase mode by connecting one of the phases to a fixed "mid-point" voltage. By replacing the fixed biased gate electrode with implants, Texas Instruments developed virtual phase technology. Evolution of the virtual phase technology is discussed in detail by [Hynecek, 1981] (see Figure 4.9).
So far only a single column of pixels has been assumed. In this type of detector, called a linear array, charge is transferred to the end of the column where it is detected. Such devices are often found in image scanners and fax machines. Of more general interest are area arrays which may contain as little as 100 columns, each of 100 pixels. At the other extreme, both in size and price, are devices such as the ST-002A CCD from SITe [Sci, 1994]. This particular commercially available device has more than 2000 columns, each with more than 4000 3-phase pixels.
The basic structure of an area array CCD is just the logical extension of that for a single column linear array. Consider first a single column CCD where the pixel width, that is the column width, is much greater than the pixel height. During manufacturing, the large single column can be split longitudinally into a number of narrower columns by the addition of potential barriers to the epitaxial layer. These barriers, called channel stops have the sole purpose of blocking the movement of charge in a direction parallel to the gate electrodes and as such define the width of the columns.
Figure 4.10: A simple area array CCD device.
Although an area array of pixels has now been defined, it is clearly not practical to directly detect the charge at the end of each column. For this reason an additional row, called a serial register, is placed across the end of the multiple columns of pixels. By application of the proper set of signals, charge from each pixel can now be detected sequentially. A simple array is shown in Figure 4.10 with the corresponding sequence of events needed to read the array following.
- Parallel transfer: Cycle the parallel clock signals, p1 to p3, so the accumulated charges are transferred down by one pixel. The charge from pixels 1 to 4 will be transferred into the serial register.
- Serial transfer: Cycle the serial clock signals, s1 to s3, to move the charge that originated in pixel 1 into the detection circuits.
- Repeat the serial transfer, to move the charge that originated in pixel 2 into the detection circuits. The same again for the charge from pixels 3 then 4.
- The whole process is then repeated to detect the charge from pixels 5 to 8 and so on until the charge from all pixels have been detected.
Step 4: Charge Detection
Figure 4.11: Simplified
charge detection circuitry.
The final stage in the operation of the CCD chip is to detect the charge and provide a suitable output signal. The method for achieving this is to simply transfer the charge onto a small capacitance and, after isolation and buffering, the change in potential across the capacitance becomes the output signal.
A simplified equivalent of the charge detection circuitry is shown in Figure 4.11 with the corresponding sequence of events following.
- Reset: The detection capacitance is briefly connected to a reference voltage to bring it’s potential to a known value. (Switch S in Figure 4.11 is briefly closed.)
- Sample: An amplified version of the CCD’s output is sampled by external signal processing circuitry.
- Charge: The serial clock signals are cycled (Gate voltage Vg in Figure 4.11 is brought low) to transfer charge onto the capacitance resulting in a change in potential of ΔV = Q/C.
- Sample: A second sample is taken. Note that it is the difference between this and the previous sample that corresponds to the desired output signal, and not the actual potential at any point in time.
- The whole process is then repeated to detect each of the charges in the serial register.
Typical output levels are usually in the order of 1 to 10 microvolts per electron of charge with a saturated pixel corresponding to a few hundred millivolts.